View MAX109EHF-D_1272210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-0795; Rev 0; 4/07
KIT ATION EVALU BLE AVAILA
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
General Description
The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a highperformance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time. The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (1014 clock cycles). This design guarantees no missing codes. The analog input is designed for both differential and single-ended use with a 500mVP-P input-voltage range. The output data is in standard LVDS format, and is demultiplexed by an internal 1:4 demultiplexer. The LVDS outputs operate from a supply-voltage range of 3V to 3.6V for compatibility with single 3V-reference systems. Control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate. The MAX109 is offered in a 256-pin Super Ball-Grid Array (SBGA) package and is specified over the extended industrial temperature range (-40C to +85C).
Features
Ultra-High-Speed, 8-Bit, 2.2Gsps ADC 2.8GHz Full-Power Analog Input Bandwidth Excellent Signal-to-Noise Performance 44.6dB SNR at fIN = 300MHz 44dB SNR at fIN = 1600MHz Superior Dynamic Range at High-IF 61.7dBc SFDR at fIN = 300MHz 50.3dBc SFDR at fIN = 1600MHz -60dBc IM3 at fIN1 = 1590MHz and fIN2 = 1610MHz 500mVP-P Differential Analog Inputs 6.8W Typical Power Including the Demultiplexer Adjustable Range for Offset, Full-Scale, and Sampling Instance 50 Differential Analog Inputs 1:4 Demultiplexed LVDS Outputs Interfaces Directly to Common FPGAs with DDR and QDR Modes
MAX109
Ordering Information
PART MAX109EHF-D TEMP RANGE -40C to +85C PINPACKAGE 256 SBGA PKG CODE H256-1
D = Dry pack.
Applications
Radar Warning Receivers (RWR) Light Detection and Ranging (LIDAR) Digital RF/IF Signal Processing Electronic Warfare (EW) Systems High-Speed Data-Acquisition Systems Digital Oscilloscopes High-Energy Physics Instrumentation ATE Systems
TOP VIEW
1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 7 8
Pin Configuration
9 10 11 12 13 14 15 16 17 18 19 20
MAX109 256-PIN SBGA PACKAGE
256-PIN SUPER BALL-GRID ARRAY
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
A[0:7]
B[0:7]
C[0:7]
D[0:7]
DOR
DCO
RSTOUT
DEMUX RESET OUTPUT DEMUX CLOCK DRIVER
PORTC
PORTD
PORTA
PORTB
DCO
DOR
QDR DEMUX CLOCK GENERATOR DDR DELAYED RESET
LOGIC CLOCK DRIVER REFERENCE AMPLIFIER 8-BIT ADC CORE
RESET PIPELINE
REFIN
QUANTIZER CLOCK DRIVER RESET INPUT DUAL LATCH T/H AMPLIFIER INPUT CLOCK BUFFER
REFOUT BANDGAP REFERENCE
RSTINN RSTINP
GNDI 50 50 50 50 TEMPERATURE MONITOR TEMPMON
VOSADJ
INP
INN
SAMPADJ CLKP
CLKCOM
CLKN
Figure 1. Functional Diagram of the MAX109
2
_______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
VCCA to GNDA ....................................................... -0.3V to +6V VCCD to GNDD ....................................................... -0.3V to +6V VCCI to GNDI ........................................................... -0.3V to +6V VCCO to GNDO ................................................... -0.3V to +3.9V VEE to GNDI ............................................................ -6V to +0.3V Between Grounds (GNDA, GNDI, GNDO, GNDD, GNDR) ................................................ -0.3V to +0.3V VCCA to VCCD ..................................................... -0.3V to +0.3V VCCA to VCCI ....................................................... -0.3V to +0.3V Differential Voltage between INP and INN ........................... 1V INP, INN to GNDI ................................................................. 1V Differential Voltage between CLKP and CLKN..................... 3V CLKP, CLKN, CLKCOM to GNDI ............................... -3V to +1V Digital LVDS Outputs to GNDO .............. -0.3V to (VCCO - 0.3V) REFIN, REFOUT to GNDR ........................-0.3V to (VCCI + 0.3V) REFOUT Current ...............................................-100A to +5mA RSTINP, RSTINN to GNDA .....................-0.3V to (VCCO + 0.3V) RSTOUTP, RSTOUTN to GNDO .............-0.3V to (VCCO + 0.3V) VOSADJ, SAMPADJ, TEMPMON to GNDI...............................-0.3V to (VCCI + 0.3V) PRN, DDR, QDR to GNDD.......................-0.3V to (VCCD + 0.3V) DELGATE0, DELGATE1 to GNDA ...........-0.3V to (VCCA + 0.3V) Continuous Power Dissipation (TA = +70C) 256-Ball SBGA (derate 74.1mW/C above +70C for a multilayer board) ................................................. 5925.9mW Operating Temperature Range MAX109EHF ...................................................-40C to +85C Thermal Resistance JA (Note 1) .......................................3C/W Operating Junction Temperature.....................................+150C Storage Temperature Range .............................-65C to +150C
MAX109
Note 1: Thermal resistance is based on a 5in x 5in multilayer board. The data sheet assumes a thermal environment of 3C/W. Thermal resistance may be different depending on airflow and heatsink cooling capabilities.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100. Specifications +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) Transfer Curve Offset (Note 2) ANALOG INPUTS (INN, INP) Common-Mode Input-Voltage Range Common-Mode Rejection Ratio (Note 3) Full-Scale Input Range (Note 2) Input Resistance Input Resistance Temperature Coefficient Input Resistance (Note 4) Input Offset Voltage VCM CMRR VFS RIN TCR VREFIN = 2.5V 470 45 Signal and offset with respect to GNDI 1 50 500 50 150 535 55 V dB mVP-P ppm/C RES INL DNL VOS (Note 8) Guaranteed no missing codes, TA = +25C (Note 8) VOSADJ control input open (Note 8) 8 -0.8 -0.8 -5.5 0.25 0.25 0 +0.8 +0.8 +5.5 Bits LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
VOS ADJUST CONTROL INPUT (VOSADJ) RVOSADJ VOS VOSADJ = 0V VOSADJ = 2.5V 25 SAMPADJ = 0 to 2.5V 25 50 -20 20 50 30 75 75 k mV mV k ps
SAMPLE ADJUST CONTROL INPUT (SAMPADJ) Input Resistance Aperture Time Adjust Range RSAMPADJ tAD
_______________________________________________________________________________________
3
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
DC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100. Specifications +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN 2.460 TYP 2.500 < 7.5 2.500 0.25 4 5 200 to 2000 -2 to +2 45 50 150 55 MAX 2.525 UNITS V mV V k REFERENCE INPUT AND OUTPUT (REFIN, REFOUT) Reference Output Voltage REFOUT Reference Output Load Regulation Reference Input Voltage Reference Input Resistance CLOCK INPUTS (CLKP, CLKN) Clock Input Amplitude Clock Input Common-Mode Range Clock Input Resistance Input Resistance Temperature Coefficient High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current LVDS INPUTS (RSTINP, RSTINN) Differential Input High Voltage Differential Input Low Voltage Minimum Common-Mode Input Voltage Maximum Common-Mode Input Voltage TEMPERATURE MEASUREMENT OUTPUT (TEMPMON) Temperature Measurement Accuracy Output Resistance Differential Output Voltage Output Offset Voltage VOD VOS T (C) = [(VTEMPMON - VGNDI) x 1303.5] 371 Measured between TEMPMON and GNDI RLOAD = 100 RLOAD = 100 250 1.10 7 0.725 400 1.28 C k mV V 1 VCCO 0.15 0.2 -0.2 V V V V RCLK TCR Peak-to-peak differential (Figure 13b) Signal and offset referenced to CLKCOM CLKP and CLKN to CLKCOM mV V ppm/C REFOUT REFIN RREFIN 0 < ISOURCE < 2.5mA
CMOS CONTROL INPUTS (DDR, QDR, PRN, DELGATE0, DELGATE1) VIH VIL IIH IIL Threshold voltage = 1.2V Threshold voltage = 1.2V VIH = 3.3V VIL = 0V -50 1.4 3.3 0.8 50 V V A A
LVDS OUTPUTS (PortA, PortB, PortC, PortD, DORP, DORN, DCOP, DCON, RSTOUTP, RSTOUTN) (Note 9)
4
_______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100. Specifications +25C guaranteed by production test, < +25C guaranteed by design and characterization. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER POWER REQUIREMENTS Analog Supply Current Positive Input Supply Current Negative Input Supply Current Digital Supply Current Output Supply Current Power Dissipation Positive Power-Supply Rejection Ratio Negative Power-Supply Rejection Ratio IVCCA IVCCI 556 125 181 291 222 6.50 (Note 5) VEE = -5.25V to -4.75V 50 50 744 168 240 408 300 8.79 mA mA mA mA mA W dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX109
IIVEEI
IVCCD IVCCO PDISS PSRRP PSRRN
AC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER ANALOG INPUT Analog Input Full-Power Bandwidth (Note 6) Gain Flatness DYNAMIC SPECIFICATIONS SNR300 SNR1000 Signal-to-Noise Ratio SNR1600 SNR2500 SNR500 SNR1600 THD300 THD1000 Total Harmonic Distortion (Note 7) THD1600 THD2500 THD500 THD1600 fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps 43.6 42.2 44.6 44.5 44.0 42.9 44.4 44.0 -55.6 -48.5 -46.6 -43.7 -49.0 -43.1 -42.5 -39.6 dBc dB BW-3dB GF 1100MHz to 2200MHz 2.8 0.3 GHz dB SYMBOL CONDITIONS MIN TYP MAX UNITS
_______________________________________________________________________________________
5
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SYMBOL SFDR300 SFDR1000 Spurious Free Dynamic Range SFDR1600 SFDR2500 SFDR500 SFDR1600 SINAD300 Signal-to-Noise-Plus-Distortion Ratio CONDITIONS fIN = 300MHz, fCLK = 2.2Gsps fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) fIN = 2500MHz, fCLK = 2.2Gsps fIN = 500MHz, fCLK = 2.5Gsps fIN = 1600MHz, fCLK = 2.5Gsps fIN = 300MHz, fCLK = 2.2Gsps 40.4 37.9 44.4 43.7 MIN TYP 61.7 51.1 50.3 45.0 53.7 44.6 44.1 43.1 42.1 40.1 43.1 40.5 -60 10-14 fCLK(MAX) tPWL tPWH tAD tAJ tSU tHD tPD1 CLK-to-DCO Propagation Delay tPD1DDR tPD1QDR tPD2 DCO-to-Data Propagation Delay tPD2DDR tPD2QDR DCO Duty Cycle (Note 8) (Note 8) DCO = fCLK / 4, CLK fall to DCO rise time DCO = fCLK / 8, DDR mode, CLK fall to DCO rise time DCO = fCLK / 16, QDR mode, CLK fall to DCO rise time DCO = fCLK / 4, DCO rise to data transition (Note 8) DCO = fCLK / 8, DDR mode, DCO rise to data transition (Note 8) DCO = fCLK / 16, QDR mode, DCO rise to data transition (Note 8) Clock mode independent -520 -520 + 2tCLK -520 + 2tCLK 2tCLK 2tCLK 45 to 55 300 250 1.6 1.6 1.6 +520 520 + 2tCLK 520 + 2tCLK % ps ns tCLK = tPWL + tPWH (Note 8) tCLK = tPWL + tPWH (Note 8) 2.2 180 180 200 0.2 Gsps ps ps ps ps ps ps dBc dB dBc MAX UNITS
SINAD1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) SINAD1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) SINAD2500 fIN = 2500MHz, fCLK = 2.2Gsps SINAD500 Third-Order Intermodulation Metastability Probability TIMING CHARACTERISTICS Maximum Sample Rate Clock Pulse-Width Low Clock Pulse-Width High Aperture Delay Aperture Jitter Reset Input Data Setup Time Reset Input Data Hold Time IM3 fIN = 500MHz, fCLK = 2.5Gsps fIN1 = 1590MHz, fIN2 = 1610MHz at -7dBFS SINAD1600 fIN = 1600MHz, fCLK = 2.5Gsps
6
_______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER LVDS Output Rise Time LVDS Output Fall Time LVDS Differential Skew PortD Data Pipeline Delay PortC Data Pipeline Delay PortB Data Pipeline Delay PortA Data Pipeline Delay SYMBOL tRDATA tFDATA tSKEW1 tPDD tPDC tPDB tPDA CONDITIONS 20% to 80%, CL < 2pF 20% to 80%, CL < 2pF Any two LVDS output signals, except DCO MIN TYP 500 500 <100 7.5 8.5 9.5 10.5 MAX UNITS ps ps ps Clock Cycles Clock Cycles Clock Cycles Clock Cycles
MAX109
Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range (FSR) is defined as 255 x slope of the line where the slope of the line is determined by the end-point code transitions. When the analog input voltage exceeds positive FSR, the output code is 11111111; when the analog input voltage is beyond the negative FSR, the output code is 00000000. Note 3: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in dB. Note 4: The offset-adjust control input is tied to an internal 1.25V reference level through a resistor. Note 5: Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCC varies from 4.75V to 5.25V. Note 6: To achieve 2.8GHz full-power bandwidth, careful board layout techniques are required. Note 7: The total harmonic distortion (THD) is computed from the second through the 15th harmonics. Note 8: Guaranteed by design and characterization. Note 9: RSTOUTP/RSTOUTN are tested for functionality.
Typical Operating Characteristics
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100. Typical values are at TJ = +105C, unless otherwise noted.)
FFT PLOT (16,384-POINT DATA RECORD)
MAX109 toc01
FFT PLOT (16,384-POINT DATA RECORD)
MAX109 toc02
FFT PLOT (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 fCLK = 2.21184GHz fIN = 999.135MHz AIN = -1.059dBFS SNR = 44.5dB SINAD = 43.3dB THD = -49.5dBc SFDR = 52.1dBc HD2 = -57.3dBc HD3 = -52.1dBc
MAX109 toc03
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0
AMPLITUDE (dB)
fCLK = 2.21184GHz fIN = 98.145MHz AIN = -0.975dBFS SNR = 45.2dB SINAD = 44.8dB THD = -55.7dBc SFDR = 57.2dBc HD2 = -69.6dBc HD3 = -57.2dBc
0 -10 -20 -30 -40 -50 -60 -70 -80 fCLK = 2.21184GHz fIN = 300.105MHz AIN = -1.034dBFS SNR = 45.1dB SINAD = 44.8dB THD = -56.2dBc SFDR = 62.4dBc HD2 = -64.4dBc HD3 = -62.7dBc
0
276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz)
-90
0
276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz)
-90
0
276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100. Typical values are at TJ = +105C, unless otherwise noted.)
FFT PLOT (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) fCLK = 2.21184GHz fIN = 1600.155MHz AIN = -0.992dBFS SNR = 44.2dB SINAD = 42.6dB THD = -47.5dBc SFDR = 51.1dBc HD2 = -51.1dBc HD3 = -52.1dBc
MAX109 toc04
FFT PLOT (16,384-POINT DATA RECORD)
MAX109 toc05
TTIMD PLOT (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 2fIN2 - fIN1 2fIN1 - fIN2 fCLK = 2.21184GHz fIN1 = 1590.165MHz fIN2 = 1610.415MHz AIN1 = AIN2 = -7.13dBFS IM3 = -60.8dBc
MAX109 toc06
0
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 fCLK = 2.49856GHz fIN = 1599.268MHz AIN = -1.059dBFS SNR = 44.1dB SINAD = 41.2dB THD = -44.4dBc SFDR = 46.1dBc HD2 = -50.1dBc HD3 = -46.1dBc
0
312.32 624.64 936.96 1249.28 156.16 468.48 780.8 1098.12 ANALOG INPUT FREQUENCY (MHz)
-90
0
276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS)
SNR 46 SNR, SINAD (dB)
MAX109 toc07
ENOB vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS)
MAX109 toc08
-THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS)
MAX109 toc09
50
8.0 7.5 7.0 ENOB (Bits)
65 60 -THD, SFDR (dBc) 55 50 45 -THD 40 35 SFDR
42 SINAD
6.5 6.0
38
34
5.5 5.0 0 500 1000 1500 fIN (MHz) 2000 2500 0 500 1000 1500 fIN (MHz) 2000 2500
30
0
500
1000 1500 fIN (MHz)
2000
2500
HD2, HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS)
MAX109 toc10
SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 2.49856Gsps, AIN = -1dBFS)
MAX109 toc11
ENOB vs. ANALOG INPUT FREQUENCY (fCLK = 2.49856Gsps, AIN = -1dBFS)
MAX109 toc12
-30 -35 -40 -45 HD2, HD3 (dBc) -50 -55 -60 -65 -70 -75 -80 0 500 1000 1500 fIN (MHz) 2000 HD2 HD3
50 SNR 46 SNR, SINAD (dB)
8.0 7.5 7.0 ENOB (Bits)
42
6.5 6.0
38
SINAD
34
5.5 5.0 0 500 1000 1500 fIN (MHz) 2000 2500 0 500 1000 1500 fIN (MHz) 2000 2500
30 2500
8
_______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100. Typical values are at TJ = +105C, unless otherwise noted.) SNR, SINAD vs. ANALOG INPUT AMPLITUDE -THD, SFDR vs. ANALOG INPUT FREQUENCY HD2, HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, fIN = 1600.1550MHz) (fCLK = 2.49856Gsps, AIN = -1dBFS) (fCLK = 2.49865Gsps, AIN = -1dBFS)
MAX109 toc13 MAX109 toc14
MAX109
-35 -40 -45 HD2, HD3 (dBc) -50 -55 -60 -65 HD2 HD3
40 35
SNR
60 -THD, SFDR (dBc) 55 50 45 -THD 40 35 0 500 1000 1500 fIN (MHz) 2000 SFDR
SINAD SNR, SINAD (dB) 30 25 20 15 10 5 0 0 500 1000 1500 fIN (MHz) 2000 2500 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) -5 0
-70 -75 -80 2500
ENOB vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz)
MAX109 to16
-THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz)
MAX109 toc17
HD2, HD3 vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz)
-25 -30 -35 HD2, HD3 (dBc) -40 -45 -50 -55 -60 -65 -70 HD2 HD3
MAX109 toc18
8.0 7.5 7.0 ENOB (Bits) 6.5 6.0 5.5 5.0 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) -5 0
60 55 50 -THD, SFDR (dBc) 45 40 35 30 25 20 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) -5 0 -THD SFDR
-20
-45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS)
-5
0
SNR, SINAD vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS)
MAX109 toc19
ENOB vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS)
MAX109 toc20
-THD, SFDR vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS)
SFDR 55 -THD, SFDR (dBc)
MAX109 toc21
50 SNR 46 SNR, SINAD (dB)
8.0 7.5 7.0 ENOB (Bits)
60
42 SINAD
50
6.5 6.0
38
45
-THD
34
5.5 5.0 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz) 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz)
40
30
35 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz)
_______________________________________________________________________________________
MAX109 toc15
65
-30
45
9
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100. Typical values are at TJ = +105C, unless otherwise noted.)
HD2, HD3 vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS)
MAX109 toc22
SNR, SINAD vs. VCCA/VCCI (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc23
-THD, SFDR vs. VCCA/VCCI (fIN = 1600.1550MHz, AIN = -1dBFS)
52 51 -THD, SFDR (dBc) 50 49 48 47 46 45 44 VCCD = 5V VCCO = 3.3V VEE = -5V 4.75 4.85 4.95 5.05 VCCA/VCCI (V) 5.15 5.25 SFDR -THD VCCA AND VCCI CONNECTED TOGETHER
MAX109 toc24
-40 -45 -50 HD2, HD3 (dBc) -55 -60 -65 -70 -75 HD2 HD3
50 48 46 SNR, SINAD (dB) 44 42 40 38 36
VCCA AND VCCI CONNECTED TOGETHER SNR
53
SINAD VCCD = 5V VCCO = 3.3V VEE = -5V 4.75 4.85 4.95 5.05 VCCA/VCCI (V) 5.15 5.25
500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz)
SNR, SINAD vs. VCCD (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc25
-THD, SFDR vs. VCCD (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc26
SNR, SINAD vs. VEE (fIN = 1600.1550MHz, AIN = -1dBFS)
48 46 SNR, SINAD (dB) VCCA = VCCI = 5V VCCD = 5V VCCO = 3.3V SNR
MAX109 toc27
50 48 46 SNR, SINAD (dB) 44 42 40 38 36 4.75 4.85 4.95 5.05 VCCD (V) 5.15 SINAD VCCA = VCCI = 5V VCCO = 3.3V VEE = -5V SNR
53 52 51 -THD, SFDR (dBc) 50 49 48 47 46 45 44 VCCA = VCCI = 5V VCCO = 3.3V VEE = -5V 4.75 4.85 4.95 5.05 VCCD (V) 5.15 SFDR -THD
50
44 42 40 38 36 SINAD
5.25
5.25
-5.25
-5.15
-5.05 -4.95 VEE (V)
-4.85
-4.75
-THD, SFDR vs. VEE (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc28
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (262,144-POINT DATA RECORD)
MAX109 toc29
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (262,144-POINT DATA RECORD)
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX109 toc30
53 52 51 -THD, SFDR (dBc) 50 49 48 47 46 45 44 -5.25 -5.15 -5.05 -4.95 VEE (V) -4.85 SFDR -THD VCCA = VCCI = 5V VCCD = 5V VCCO = 3.3V
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
-4.75
0
32
64
96
128 160 192 224 256
0
32
64
96
128 160 192 224 256
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
10
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100. Typical values are at TJ = +105C, unless otherwise noted.) SMALL-SIGNAL INPUT BANDWIDTH FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY REFERENCE VOLTAGE vs. VCCA/VCCI vs. ANALOG INPUT FREQUENCY (AIN = -1dBFS) (AIN = -20dBFS)
MAX109 toc31 MAX109 toc32
MAX109
0 -1 GAIN (dB) -2 -3 -4 -5 -6 10 100 1000 ANALOG INPUT FREQUENCY (MHz)
0 -1
2.4985 2.4975 VREFOUT (V) 2.4965 2.4955 2.4945 2.4935
VCCA AND VCCI CONNECTED TOGETHER VCCO = 3.3V VCCD = 5V VEE = -5V
GAIN (dB)
-2 -3 -4 -5
10,000
-6
10
100 1000 ANALOG INPUT FREQUENCY (MHz)
10,000
2.4925
4.75
4.85
4.95 5.05 VCCA/VCCI (V)
5.15
5.25
ANALOG/DIGITAL POWER DISSIPATION vs. VCCA/VCCI/VCCD/-VEE (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc34
OUTPUT DRIVER POWER DISSIPATION vs. VCCO (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc35
SNR, SINAD vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc36
6800 VCCO = 3.3V VCCA = VCCI = VCCD = 4.75V to 5V VEE = -4.75V to -5.25V
900 VCCO = 3V to 3.6V VCCA = VCCI = VCCD = 5V VEE = -5V
45 SINAD SNR 41
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
6500
850
43 SNR, SINAD (dB)
6200
800
5900
750
39
5600
700
37
5300 4.75 4.85 4.95 5.05 5.15 VCCA/VCCI/VCCD/-VEE (V) 5.25
650
3.0
3.1
3.2
3.3 3.4 VCCO (V)
3.5
3.6
35
-40 [-22.1]
-15 [7.5]
10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (C) [DIE TEMPERATURE (C)]
85 [125.9]
MAX109 toc38
MAX109 toc37
7.25 7.00
52 50 -THD, SFDR (dBc) 48 46 44 42 40 38 -THD SFDR
-46 HD2 HD2, HD3 (dBc) -48 -50 HD3 -52 -54 -56
ENOB (Bits)
6.75 6.50 6.25 6.00 5.75 5.50 -40 [-22.1] -15 [7.5] 10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (C) [DIE TEMPERATURE (C)] 85 [125.9]
-40 [-22.1]
-15 [7.5]
10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (C) [DIE TEMPERATURE (C)]
85 [125.9]
-40 [-22.1]
-15 [7.5]
10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (C) [DIE TEMPERATURE (C)]
85 [125.9]
______________________________________________________________________________________
11
MAX109 toc39
7.50
ENOB vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS)
54
-THD, SFDR vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS)
-44
HD2, HD3 vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS)
MAX109 toc33
1
1
2.4995
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Pin Description
PIN A1, A2, B1, B2, C1-C5, D5, L1-L4, U5, V1-V4, W1, W2, Y1, Y2 A3, A4, B3, B4, D1-D4, K1-K4, U1-U4, W3, W4, Y3, Y4 A9, B9, C10, D10, U10, V10, W10, Y10 A10, B10, C11, D11, U11, V11, W11, Y11 A11, A19, B11, B18, C12, C18, D12, D18, E17, U17, V17, W17, Y17, U12, V12, W12, Y12 A12, A18, B12, B13, B17, C13, C17, D13, D17, U13, U16, V13, V16, W13, W16, Y13, Y16 H17-H20, P17-P20, U15, V15, W15, Y15 E18, F17-F20, J17, J18, J19, N17, N18, N19, T17-T20, U18 D19, D20, E19, E20, G17-G20, J20, K17, K18, K19, L17-L20, M17, M18, M19, N20, R17-R20, U14, U19, U20, V14, V19, V20, W14, Y14 NAME FUNCTION
VCCO
LVDS Output Power Supply. Accepts an input-voltage range of 3.3V 10%.
GNDO
LVDS Output Ground. Ground connection for LVDS output drivers.
VCCD
Digital Logic Power Supply. Accepts an input-voltage range of 5V 5%.
GNDD
Digital Ground. Ground connection for digital logic circuitry.
VCCA
Analog Supply Voltage for Comparator Array. Accepts an input-voltage range of 5V 5%.
GNDA
Analog Ground. Ground connection for comparator array.
VCCI
Analog Supply Voltage. Analog power supply (positive rail) for T/H amplifier. Accepts an inputvoltage range of 5V 5%.
VEE
Negative Power Supply. Analog power supply (negative rail) for the T/H amplifier. Accepts an input-voltage range of -5V 5%.
GNDI
Analog Ground. Ground connection for the T/H amplifier.
12
______________________________________________________________________________________
PIN NAME
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Pin Description (continued)
PIN A14 A16 A13, A15, A17, B14, B15, B16, C14, C15, C16, D14, D15, D16 B20 B19 C19 NAME CLKP CLKN FUNCTION True/Positive Sampling Clock Input. Positive terminal for differential input configuration. Complementary/Negative Sampling Clock Input. Negative terminal for differential input configuration.
MAX109
CLKCOM
50 Clock Termination Return
SAMPADJ DELGATE1 DELGATE0
Sampling Point Adjustment Input. Allows the user to adjust the sampling event by applying a voltage between 0 to 2.5V to this input. Timing Delay Adjustment. Coarse (MSB) adjustment for the timing between T/H amplifier and quantizer. Timing Delay Adjustment. Coarse (LSB) adjustment for the timing between T/H amplifier and quantizer. Reference Voltage Input. For applications requiring improved gain performance and referencevoltage adjustability, allows the user to utilize the REFIN input by applying a more accurate and adjustable reference source. This input accepts an input-voltage range of 2.5V 10%. Internal Reference Output. Connect to REFIN, if using the internal 2.5V bandgap reference. Bandgap Reference Ground. Ground connection for the internal bandgap reference and its related circuitry. True/Positive Analog Input Terminal. For single-ended signals, apply signal to INP and reverseterminate INN to GNDI with a 50 resistor. Complementary/Negative Analog Input Terminal. For singled-ended signals, reverse-terminate INN to GNDI with a 50 resistor and apply the signal directly to INP. Analog Voltage Input to Adjust the Converter Offset. This input accepts an input-voltage range of 0 to 2.5V allowing the offset to be adjusted at roughly 10 LSB. True/Positive LVDS Data-Overrange Output Bit. This output flags over- and under-range conditions of the data converter. Complementary/Negative LVDS Data-Overrange Output Bit. This output flags over- and underrange conditions on the data converter. True/Positive LVDS Data Clock Output. Synchronize user-supplied data-capture board or dataacquisition system to this clock. Complementary/Negative LVDS Data Clock Output. Synchronize user-supplied data-capture board or data-acquisition system to this clock.
Y20 Y19 V18, W18, Y18 M20 K20 W20 M4 M3 M2 M1
REFIN REFOUT GNDR INP INN VOSADJ DORP DORN DCOP DCON
______________________________________________________________________________________
PIN NAME
13
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Pin Description (continued)
PIN Y5 W5 V5 D9 C9 B5 A5 B8 A8 B6 A6 F2 F1 H2 H1 N2 N1 R2 R1 W6 Y6 W8 Y8 D8 C8 D6 C6 F4 F3 H4 H3 N4 N3 R4 NAME QDR DDR PRN RSTINP RSTINN RSTOUTP RSTOUTN D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N D1P D1N D0P D0N C7P C7N C6P C6N C5P C5N C4P C4N C3P C3N C2P FUNCTION Quad Data Rate Input (CMOS). Connect to GNDD for the default data rate to be applied. Connect to VCCD to achieve four times the specified data rate. Double Data Rate Input (CMOS). Connect to GNDD for the standard data rate to be applied. Connect to VCCD to achieve two times the specified data rate. Pseudorandom Number Generator Enable Input (CMOS). When enabled, pseudorandom patterns appear on all four LVDS output ports (PortA, PortB, PortC, and PortD). True/Positive Reset Input Complementary/Negative Reset Input True/Positive LVDS Reset Output Complementary LVDS Reset Output True/Positive Output Bit D7P, PortD, Bit 7 Complementary/Negative Output Bit D7N, PortD, Bit 7 True/Positive Output Bit D6P, PortD, Bit 6 Complementary/Negative Output Bit D6N, PortD, Bit 6 True/Positive Output Bit D5P, PortD, Bit 5 Complementary/Negative Output Bit D5N, PortD, Bit 5 True/Positive Output Bit D4P, PortD, Bit 4 Complementary/Negative Output Bit D4N, PortD, Bit 4 True/Positive Output Bit D3P, PortD, Bit 3 Complementary/Negative Output Bit D3N, PortD, Bit 3 True/Positive Output Bit D2P, PortD, Bit 2 Complementary/Negative Output Bit D2N, PortD, Bit 2 True/Positive Output Bit D1P, PortD, Bit 1 Complementary/Negative Output Bit D1N, PortD, Bit 1 True/Positive Output Bit D0P, PortD, Bit 0 Complementary/Negative Output Bit, D0N, PortD, Bit 0 True/Positive Output Bit C7P, PortC, Bit 7 Complementary/Negative Output Bit C7N, PortC, Bit 7 True/Positive Output Bit C6P, PortC, Bit 6 Complementary/Negative Output Bit C6N, PortC, Bit 6 True/Positive Output Bit C5P, PortC, Bit 5 Complementary/Negative Output Bit C5N, PortC, Bit 5 True/Positive Output Bit C4P, PortC, Bit 4 Complementary/Negative Output Bit C4N, PortC, Bit 4 True/Positive Output Bit C3P, PortC, Bit 3 Complementary/Negative Output Bit C3N, PortC, Bit 3 True/Positive Output Bit C2P, PortC, Bit 2
14
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Pin Description (continued)
PIN R3 U6 V6 U8 V8 B7 A7 E2 E1 G2 G1 J2 J1 P2 P1 T2 T1 W7 Y7 W9 Y9 D7 C7 E4 E3 G4 G3 J4 J3 P4 P3 T4 T3 NAME C2N C1P C1N C0P C0N B7P B7N B6P B6N B5P B5N B4P B4N B3P B3N B2P B2N B1P B1N B0P B0N A7P A7N A6P A6N A5P A5N A4P A4N A3P A3N A2P A2N True/Positive Output Bit C1P, PortC, Bit 1 Complementary/Negative Output Bit C1N, PortC, Bit 1 True/Positive Output Bit C0P, PortC, Bit 0 Complementary/Negative Output Bit C0N, PortC, Bit 0 True/Positive Output Bit B7P, PortB, Bit 7 Complementary/Negative Output Bit B7N, PortB, Bit 7 True/Positive Output Bit B6P, PortB, Bit, 6 Complementary/Negative Output Bit B6N, PortB, Bit 6 True/Positive Output Bit B5P, PortB, Bit 5 Complementary/Negative Output Bit B5N, PortB, Bit 5 True/Positive Output Bit B4P, PortB, Bit 4 Complementary/Negative Output Bit B4N, PortB, Bit 4 True/Positive Output Bit B3P, PortB, Bit 3 Complementary/Negative Output Bit B3N, PortB, Bit 3 True/Positive Output Bit B2P, PortB, Bit 2 Complementary/Negative Output Bit B2N, PortB, Bit 2 True/Positive Output Bit B1P, PortB, Bit 1 Complementary/Negative Output Bit B1N, PortB, Bit 1 True/Positive Output Bit B0P, PortB, Bit 0 Complementary/Negative Output Bit B0N, PortB, Bit 0 True/Positive Output Bit A7P, PortA, Bit 7 Complementary/Negative Output Bit A7N, PortA, Bit 7 True/Positive Output Bit A6P, PortA, Bit 6 Complementary/Negative Output Bit A6N, PortA, Bit 6 True/Positive Output Bit A5P, PortA, Bit 5 Complementary/Negative Output Bit A5N, PortA, Bit 5 True/Positive Output Bit A4P, PortA, Bit 4 Complementary/Negative Output Bit A4N, PortA, Bit 4 True/Positive Output Bit A3P, PortA, Bit 3 Complementary/Negative Output Bit A3N, PortA, Bit 3 True/Positive Output Bit A2P, PortA, Bit 2 Complementary/Negative Output Bit A2N, PortA, Bit 2 FUNCTION Complementary/Negative Output Bit C2N, PortC, Bit 2
MAX109
______________________________________________________________________________________
15
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Pin Description (continued)
PIN U7 V7 U9 V9 W19 A20, C20 NAME A1P A1N A0P A0N T.P. True/Positive Output Bit A1P, PortA, Bit 1 Complementary/Negative Output Bit A1N, PortA, Bit 1 True/Positive Output Bit A0P, PortA, Bit 0 Complementary/Negative Output Bit A0N, PortA, Bit 0 Test Point. Do not connect. FUNCTION
TEMPMON Temperature Monitor Output. Resulting output voltage corresponds to die temperature.
Detailed Description
The MAX109 is an 8-bit, 2.2Gsps flash analog-to-digital converter (ADC) with an on-chip T/H amplifier and 1:4 demultiplexed high-speed LVDS outputs. The ADC (Figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states and ensures no error exceeds a maximum of 1 LSB. An integrated 1:4 output demultiplexer simplifies interfacing to the part by reducing the output data rate to one-quarter the sampling clock rate. This demultiplexer circuit has integrated reset capabilities that allow multiple MAX109 converters to be time-interleaved to achieve higher effective sampling rates. When clocked at 2.2Gsps, the MAX109 provides a typical effective number of bits (ENOB) of 6.9 bits at an analog input frequency of 1600MHz. The MAX109 analog input is designed for both differential and single-ended use with a 500mVP-P full-scale input range. In addition, this fast ADC features an on-chip 2.5V precision bandgap reference. In order to improve the MAX109 gain error further, an external reference may be used (see the Internal Reference section).
OVERRANGE + 255 255 254 DIGITAL OUTPUT OVERRANGE
129 128 127 126 3 2 1 0 (-FS + 1 LSB) ANALOG INPUT (+FS - 1 LSB) +FS 0
Figure 2. Ideal Transfer Function
On-Chip Track/Hold Amplifier
As with all ADCs, if the input waveform is changing rapidly during conversion, ENOB and signal-to-noise ratio (SNR) specifications will degrade. The MAX109's on-chip, wide-bandwidth (2.8GHz) T/H amplifier reduces this effect and increases the ENOB performance significantly, allowing precise capture of fastchanging analog data at high conversion rates. The T/H amplifier accepts and buffers both DC- and AC-coupled analog input signals and allows a full-scale signal input range of 500mVP-P. The T/H amplifier's differential 50 input termination simplifies interfacing to the MAX109 with controlled impedance lines. Figure 3 shows a simplified diagram of the T/H amplifier stage internal to the MAX109.
Principle of Operation
The architecture of the MAX109 provides the fastest multibit conversion of all common integrated ADC designs. The key to its architecture is an innovative, high-performance comparator design. The MAX109 quantizer and its encoding logic translate the comparator outputs into a parallel 8-bit output code and pass the binary code on to the 1:4 demultiplexer. Four separate ports (PortA, PortB, PortC, and PortD) output true LVDS data at speeds of up to 550Msps per port (depending on how the demultiplexer section is set on the MAX109). The ideal transfer function appears in Figure 2.
16
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Aperture Width, Aperture Jitter, and Aperture Delay Aperture width (tAW) is the time the T/H circuit requires to disconnect the hold capacitor from the input circuit (e.g., to turn off the sampling bridge and put the T/H unit in hold mode). Aperture jitter (tAJ) is the sample-tosample variation in the time between the samples. Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample event is occurring (Figure 4).
MAX109
SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN). INP INN 50 50
INPUT AMPLIFIER T/H
BUFFER AMPLIFIER
TO COMPARATORS CHOLD GNDI CLOCK SPLITTER 50 50 TO COMPARATORS
Clock System
The MAX109 clock signals are terminated with 50 to the CLKCOM pin. The clock system provides clock signals, T/H amplifier, quantizer, and all back-end digital blocks. The MAX109 also produces a digitized output clock for synchronization with external FPGA or datacapture devices. Note that there is a 1.6ns delay between the clock input (CLKP/CLKN) and its digitized output representation (DCOP/DCON).
GNDI CLKP CLKN
CLKCOM
Figure 3. Internal Structure of the 3.2GHz T/H Amplifier
CLKN CLKP tAW ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Sampling Point Adjustment (SAMPADJ) The proper sampling point can be adjusted by utilizing SAMPADJ as the control line. SAMPADJ accepts an input-voltage range of 0 to 2.5V, correlating with up to 32ps timing adjustment. The nominal open-circuit voltage corresponds to the minimum sampling delay. With an input resistance RSAMPADJ of typically 50k, this pin can be adjusted externally with a 10k potentiometer connected between REFOUT and GNDI to adjust for the proper sampling point. T/H Amplifier to Quantizer Capture Point Adjustment (DELGATE0, DELGATE1) Another important feature of the MAX109, is the selection of the proper quantizer capture point between the T/H amplifier and the ADC core. Depending on the selected sampling speed for the application, two control lines can be utilized to set the proper capture point between these two circuits. DELGATE0 (LSB) and DELGATE1 (MSB) set the coarse timing of the proper capture point. Using these control lines allow the user to adjust the time after which the quantizer latches held data from the T/H amplifier between 25ps and 50ps (Table 1). This timing feature enables the MAX109 T/H amplifier to settle its output properly before the quantizer captures and digitizes the data, thereby achieving the best dynamic performance for any application.
T/H
TRACK
HOLD TRACK APERTURE DELAY (tAD) APERTURE WIDTH (tAW) APERTURE JITTER (tAJ)
Figure 4. T/H Aperture Timing
Aperture width, delay, and jitter are parameters that affect the dynamic performance of high-speed converters. Aperture jitter, in particular, directly influences SNR and limits the maximum slew rate (dV/dt) that can be digitized without contributing significant errors. The MAX109's innovative T/H amplifier design limits aperture jitter typically to 0.2ps.
______________________________________________________________________________________
17
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Table 1. Timing Adjustments for T/H Amplifier and Quantizer
DELGATE1 DELGATE0 TIME DELAY BETWEEN T/H AND QUANTIZER 25ps 50ps RECOMMENDED FOR CLOCK SPEEDS OF fCLK = 2.2Gsps to 2.5Gsps fCLK = 1.75Gsps to 2.2Gsps
CMFB VCCO GNDO
VCCO AOP-A7P BOP-B7P COP-C7P DOP-D7P DCOP RSTOUTP AON-A7N BON-B7N CON-C7N DON-D7N DCON RSTOUTN
0 1
1 0
Internal Reference
The MAX109 features an on-chip 2.5V precision bandgap reference used to generate the full-scale range for the data converter. Connecting REFIN with REFOUT applies the reference output to the positive input of the reference buffer. The buffer's negative input is internally connected to GNDR. It is recommended that GNDR be connected to GNDI on the user's application board. If required, REFOUT can source up to 2.5mA to supply other external devices. Additionally, an adjustable external reference can be used to adjust the ADC's fullscale range. To use an external reference supply, connect a high-precision bandgap reference to the REFIN pin and leave the REFOUT pin floating. REFIN has a typical input resistance RREFIN of 5k and accepts input voltages of 2.5V 10%.
GNDO CMFB: COMMON-MODE FEEDBACK
Figure 5. Simplified LVDS Output Circuitry
Table 2. Data Rate Selection for Demultiplexer Operation
DDR QDR 0 1 1 X 0 1 DEMULTIPLEXER OPERATION SDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port DDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port QDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port DCO SPEED fCLK / 4 fCLK / 8 fCLK / 16
Digital LVDS Outputs
The MAX109 provides data in offset binary format to differential LVDS outputs on four output ports (PortA, PortB, PortC, and PortD). A simplified circuit schematic of the LVDS output cells is shown in Figure 5. All LVDS outputs are powered from the output driver supply V CC O, which can be operated at 3.3V 10%. The MAX109 LVDS outputs provide a differential outputvoltage swing of 600mVP-P with a common-mode voltage of approximately 1.2V, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100.
X = Do not care.
negative full scale (-FS). The DORP/DORN transitions high/low whenever any of the four output ports (PortA, PortB, PortC, and PortD) display out-of-range data. DORP/DORN features the same latency as the ADC output data and is demultiplexed in a similar fashion, so that this out-of-range signal and the data samples are time-aligned.
Data Out-of-Range Operation (DORP, DORN)
A single differential output pair (DORP, DORN) is provided to flag an out-of-range condition, if the applied signal is outside the allowable input range, where outof-range is above positive full scale (+FS) or below
Demultiplexer Operation
The MAX109's internal 1:4 demultiplexer spreads the ADC core's 8-bit data across 32 true LVDS outputs and allows for easy data capture in three different modes. Two TTL/CMOS-compatible inputs are utilized to create the different modes: SDR (standard data rate), DDR
18
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP tPD1 DCON DCOP
tPWH
tPWL
tCLK
SAMPLE HERE PORTA DATA N+1
tPD2 N+5
PORTB DATA
N+2
N+6
PORTC DATA
N+3
N+7
PORTD DATA
N
N+4
N+8
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
Figure 6. Timing Diagram for SDR Mode, fCLK / 4 Mode
(double data rate), and QDR (quadruple data rate). Setting these two bits for different modes allows the user to update and process the outputs at one-quarter (SDR mode), one-eighth (DDR mode), or one-sixteenth (QDR mode) the sampling clock (Table 2), relaxing the need for an ultra-fast FPGA or data-capture interface. Data is presented on all four ports of the converterdemultiplexer circuit outputs. Note that there is a data latency between the sampled data and each of the output ports. The data latency is 10.5 clock cycles for PortA, 9.5 clock cycles for PortB, 8.5 clock cycles for PortC, and 7.5 clock cycles for PortD. This holds true for all demultiplexer modes. Figures 6, 7, and 8 display the demultiplexer timing for fCLK / 4, fCLK / 8, and fCLK / 16 modes.
Table 3. Pseudorandom Number Generator Patterns
CODE 1 2 3 4 5 6 7 8 9 10 -- -- 250 251 252 253 254 255 OUTPUT PRN PATTERN 00000001 00000010 00000100 00001000 00010001 00100011 01000111 10001110 00011100 00111000 -- -- 00110100 01101000 11010000 10100000 01000000 10000000
Pseudorandom Number (PRN) Generator
The MAX109 features a PRN generator that enables the user to test the demultiplexed digital outputs at full clock speed and with a known test pattern. The PRN generator is a combination of shift register and feedback logic with 255 states. When PRN is high, the inter-
______________________________________________________________________________________
19
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP tPD1DDR DCON DCOP SAMPLE HERE PORTA DATA N+1 N+5 tPD2DDR
PORTB DATA
N+2
N+6
PORTC DATA
N+3
N+7
PORTD DATA
N
N+4
N+8
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
Figure 7. Timing Diagram for DDR Mode, fCLK / 8 Mode
ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP tPD1QDR DCON DCOP FROM DLL IN FPGA PORTA DATA SAMPLE HERE N+1 N+5 tPD2QDR
PORTB DATA
N+2
N+6
PORTC DATA
N+3
N+7
PORTD DATA
N
N+4
N+8
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
Figure 8. Timing Diagram for QDR Mode, fCLK / 16 Mode
20 ______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
+250mV 500mVP-P FS ANALOG INPUT RANGE -250mV VIN = 250mV INP
500mV INN
0V
nal shift register is enabled and multiplexed with the input of the 1:4 demultiplexer, replacing the quantizer 8-bit output. The test pattern consists of 8 bits. Table 3 depicts the composition of the first and last steps of the PRN pattern. The entire look-up table can be downloaded from the Maxim website at www.maxim-ic.com.
t
MAX109
Applications Information
Single-Ended Analog Inputs
The MAX109 is designed to work at full speed for both single-ended and differential analog inputs; however, for optimum dynamic performance it is recommended that the inputs are driven differentially. Inputs INP and INN feature on-chip, laser-trimmed 50 termination resistors. In a typical single-ended configuration, the analog input signal (Figure 9) enters the T/H amplifier stage at the in-phase input (INP), while the inverted phase input (INN) is reverse-terminated to GNDI with an external 50 resistor. Single-ended operation allows for an input amplitude of 500mVP-P. Table 4 shows a selection of input voltages and their corresponding output codes for single-ended operation.
Figure 9. Single-Ended Analog Input Signal Swing
INP +125mV 250mV FS ANALOG INPUT RANGE -125mV 250mV -250mV INN
0V
t
Figure 10. Differential Analog Input Signal Swing
REFOUT
Differential Analog Inputs
POTENTIOMETER 10k GNDI VOSADJ
Figure 11. Offset Adjustment Circuit
CLKP 50 CLKCOM 50 CLKN GNDI 1V
To obtain a full-scale digital output with differential input drive (Figure 10), 250mVP-P must be applied between INP and INN (INP = 125mV and INN = -125mV). Midscale digital output codes (01111111 or 10000000) occur when there is no voltage difference between INP and INN. For a zero-scale digital output code, the inphase INP input must see -125mV and the inverted input INN must see 125mV. A differential input drive is recommended for best performance. Table 5 represents a selection of differential input voltages and their corresponding output codes.
Offset Adjust
The MAX109 provides a control input (VOSADJ) to compensate for system offsets. The offset adjust input is a self-biased voltage-divider from the internal 2.5V precision reference. The nominal open-circuit voltage is one-half the reference voltage. With an input resistance (RVOSADJ) of typically 50k, VOSADJ can be driven with an external 10k potentiometer (Figure 11) connected between REFOUT and GNDI to correct for offset errors. For stabilizing purposes, decouple this output with a 0.01F capacitor to GNDI. VOSADJ allows for a typical offset adjustment of 10 LSB.
SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN). VEE
Clock Operation
The MAX109 clock inputs are designed for either single-ended or differential operation (Figure 12) with flexi21
Figure 12. Clock Input Structure
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Table 4. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog Input
IN-PHASE/TRUE INPUT (INP) 250mV 250mV - 1 LSB 0 -250mV + 1 LSB -250mV <-250mV INVERTED/COMPLEMENTARY INPUT (INN) 0 0 0 0 0 0 OUT-OF-RANGE BIT (DORP/DORN) 1 0 0 0 0 1 OUTPUT CODE 11111111 (full scale) 11111111 10000000 toggles 01111111 00000001 00000000 (zero scale) 00000000 (out of range)
Table 5. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
IN-PHASE/TRUE INPUT (INP) 125mV 125mV - 0.5 LSB 0 -125mV + 0.5 LSB -125mV <-125mV INVERTED/COMPLEMENTARY INPUT (INN) -125mV -125mV + 0.5 LSB 0 125mV - 0.5 LSB 125mV >+125mV OUT-OF-RANGE BIT (DORP/DORN) 1 0 0 0 0 1 OUTPUT CODE 11111111 (full scale) 11111111 10000000 toggles 01111111 00000001 00000000 (zero scale) 00000000 (out of range)
Table 6. Driving Options for DC-Coupled Clock
CLOCK DRIVE Single-ended sine wave Differential sine wave Single-ended ECL Differential ECL CLKP -10dBm to +15dBm -10dBm to +10dBm ECL drive ECL drive CLKN Externally terminated to GNDI with 50 -10dBm to +10dBm -1.3V ECL drive CLKCOM GNDI GNDI -2V -2V REFERENCE Figure 13a Figure 13b Figure 13c Figure 13d
Table 7. Demultiplexer and Reset Operations
SIGNAL/PIN NAME CLKP/CLKN DCOP/DCON RSTINP/RSTINN RSTOUTP/RSTOUTN TYPE Sampling clock inputs LVDS outputs LVDS inputs LVDS outputs FUNCTIONAL DESCRIPTION Master ADC timing signal. The ADC samples on the rising edge of CLKP. Data clock output (LVDS). Output data changes on the rising edge of DCOP. Demultiplexer reset input signals. Resets the internal demultiplexer when asserted. Reset outputs for synchronizing the resets of multiple external devices.
ble input drive requirements. Each clock input is terminated with an on-chip, laser-trimmed 50 resistor to CLKCOM (clock-termination return). The CLKCOM termination voltage can be connected anywhere between ground and -2V for compatibility with standard-ECL drive levels. The clock inputs are internally buffered with a preamplifier to ensure proper operation of the data converter, even with small-amplitude sine-wave sources. The MAX109 was designed for single-ended, low-phase
noise sine-wave clock signals with as little as 100mV amplitude (-10dBm), thereby eliminating the need for an external ECL clock buffer and its added jitter.
Single-Ended Clock Inputs (Sine-Wave Drive) Excellent performance is obtained by AC- or DC-coupling a low-phase-noise sine-wave source into a single clock input (Figure 13a, Table 6). For proper DC balance, the undriven clock input should be externally
22
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
+0.5V
CLKP CLKN = 0V
-0.5V NOTE: CLKCOM = 0V
t
Differential Clock Inputs (Sine-Wave Drive) The advantages of differential clock drive (Figure 13b, Table 6) can be obtained by using an appropriate balun transformer to convert single-ended sine-wave sources into differential drives. The precision on-chip, laser-trimmed 50 clock-termination resistors ensure excellent amplitude matching. See the Single-Ended Clock Inputs (Sine-Wave Drive) section for proper input amplitude requirements. Single-Ended Clock Inputs (ECL Drive) Configure the MAX109 for single-ended ECL clock drive by connecting the clock inputs as shown in Figure 13c and Table 6. A well-bypassed VBB supply (-1.3V) is essential to avoid coupling noise into the undriven clock input, which would degrade dynamic performance. Differential Clock Inputs (ECL Drive) Drive the MAX109 from a standard differential ECL clock source (Figure 13d, Table 6) by setting the clock termination voltage at CLKCOM to -2V. Bypass the clock termination return (CLKCOM) as close to the ADC as possible with a 0.01F capacitor connected to GNDI.
Figure 13a. Single-Ended Clock Input--Sine-Wave Drive
CLKP +0.5V CLKN
-0.5V NOTE: CLKCOM = 0V
t
Figure 13b. Differential Clock Input--Sine-Wave Drive
CLKP CLKN = -1.3V
-0.8V
Demultiplexer Reset Operation
The MAX109 features an internal 1:4 demultiplexer that reduces the data rate of the output digital data to onequarter the sample clock rate. A reset for the demultiplexer is necessary when interleaving multiple MAX109 converters and/or synchronizing external demultiplexers. The simplified block diagram of Figure 1 shows that the demultiplexer reset signal path consists of four main circuit blocks. From input to output, they are the reset input dual latch, the reset pipeline, the demultiplexer clock generator, and the reset output. The signals associated with the demultiplexer-reset operation and the control of this section are listed in Table 7.
-1.8V NOTE: CLKCOM = -2V
t
Figure 13c. Single-Ended Clock Input--ECL Drive
CLKP -0.8V CLKN
-1.8V NOTE: CLKCOM = -2V
t
Figure 13d. Differential Clock Input--ECL Drive
50 reverse-terminated to GNDI. The dynamic performance of the data converter is essentially unaffected by clock-drive power levels from -10dBm to +10dBm. The MAX109 dynamic performance specifications are determined by a single-ended clock drive of 10dBm. To avoid saturation of the input amplifier stage, limit the clock power level to a maximum of 15dBm.
Reset Input Dual Latch The reset input dual-latch circuit block accepts LVDS reset inputs. For applications that do not require a synchronizing reset, the reset inputs may be left open. Figure 14 shows a simplified schematic of the reset input structure. To latch the reset input data properly, the setup time (tSU) and the data-hold time (tHD) must be met with respect to the rising edge of the sample clock. The timing diagram of Figure 15 shows the timing relationship of the reset input and sampling clock. Reset Pipeline The next section in the reset signal path is the reset pipeline. This block adds clock cycles of latency to the
23
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
VCCO
nization is necessary to set the order of output samples between the devices. Resetting the converters accomplishes this synchronization. The reset signal is used to force the internal counter in the demultiplexer clockgenerator block to a known phase state.
500 RSTINP
500 RSTINN 100k SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN)
VCCO
GNDD
Figure 14. Reset Circuitry--Input Structure
RSTINP 50% RSTINN 50%
tSU
tHD CLKP 50% CLKN
Figure 15. Timing Relationship between Sampling Clock and Reset Input
Reset Output Finally, the reset signal is presented in true LVDS format to the last block of the reset signal path. RSTOUT outputs the time-aligned reset signal, used for resetting additional external demultiplexers in applications that need further output data-rate reduction. Many demultiplexer devices require their reset signal to be asserted for several clock cycles while they are clocked. To accomplish this, the MAX109 DCO clock will continue to toggle while RSTOUT is asserted. When a single MAX109 device is used, no synchronizing reset is required because the order of the samples in the output ports remains unchanged, regardless of the phase of the DCO clock. In all modes, RSTOUT is delayed by 7.5 clock cycles, starting with the first rising edge of CLKP following the falling edge of the RSTINP signal. With the next reset cycle PortD data shows the expected and proper data on the output, while the remaining three ports (PortA, PortB, and PortC) keep their previous data, which may or may not be swallowed, depending on the power-up state of the demultiplexer clock generator. With the next cycle, the right data is presented for all four ports in the proper order. The aforementioned reset output and data-reset operation is valid for SDR, DDR, and QDR modes.
reset signal to match the latency of the converted analog data through the ADC. In this way, when reset data arrives at the RSTOUTP/RSTOUTN LVDS output it will be time-aligned with the analog data present in data ports PortA, PortB, PortC, and PortD at the time the reset input was deasserted.
Die Temperature Measurement
The die temperature of the MAX109 can be determined by monitoring the voltage V TEMPMON between the TEMPMON output and GNDI. The corresponding voltage is proportional to the actual die temperature of the converter and can be calculated as follows: TDIE (C) = [(VTEMPMON - VGNDI) x 1303.5] - 371 The MAX109 exhibits a typical TEMPMON voltage of 0.35V, resulting in an overall die temperature of +90C. The converter's die temperature can be lowered considerably by cooling the MAX109 with a properly sized heatsink. Adding airflow across the part with a small fan can further lower the die temperature, making the system more thermally manageable and stable.
Demultiplexer Clock Generator The demultiplexer clock generator creates the clocks required for the different modes of demultiplexer operation. DDR and QDR control the demultiplexed mode selection, as described in Table 2. The timing diagrams in Figures 6, 7, and 8 show the output timing and data alignment for SDR, DDR, and QDR modes, respectively. The phase relationship between the sampling clock at the CLKP/CLKN inputs and the DCO clock at the DCOP/DCON outputs is random at device power-up. Reset all MAX109 devices to a known DCO phase after initial power-up for applications such as interleaving, where two or more MAX109 devices are used to achieve higher effective sampling rates. This synchro-
Thermal Management
Depending on the application environment for the SBGA-packaged MAX109, the user can apply an external heatsink with integrated fan to the package after board assembly. Existing open-tooled heatsinks with
24
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP RESET INPUT DCON DCOP
RSTINN tSU RSTINP
tHD
SAMPLE HERE PORTA DATA N+5
PORTB DATA
N+6
PORTC DATA
N+7
PORTD DATA RSTOUTN RESETOUT DATA PORT RSTOUTP THE GRAY AREAS INDICATE A POWER-UP DEPENDENT STATE, WHICH IS UNKNOWN AT THE TIME THE RESET IS BEING ASSERTED.
N+4
N+8
Figure 16. Reset Output Timing in Demultiplexed SDR Mode
integrated fans are available from Co-Fan USA (e.g., the 30-1101-02 model, which is used on the evaluation kit of the MAX109). This particular heatsink with integrated fan is available with pre-applied adhesive for easy package mounting.
puts, should be routed on 50 microstrip lines, such as those employed on the MAX109 evaluation kit. The MAX109 has separate analog and digital powersupply inputs: * VEE (-5V) is the analog and substrate supply * VCCI (5V) to power the T/H amplifier, clock distribution, bandgap reference, and reference amplifier * VCCA (5V) to supply the ADC's comparator array * VCCO (3.3V) to establish power for all LVDS-based circuit sections * VCCD (5V) to supply all logic circuits of the data converter The MAX109 VEE supply contacts must not be left open while the part is being powered up. To avoid this condition, add a high-speed Schottky diode (such as a Motorola 1N5817) between VEE and GNDI. This diode prevents the device substrate from forward biasing, which could cause latchup. All supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PCB. For best performance, bypass all power supplies to the appropriate grounds with a 330F and 33F tantalum capacitor to filter powersupply noise, in parallel with 0.1F capacitors and highquality 0.01F ceramic chip capacitors. Each power
25
Bypassing/Layout/Power Supply
Grounding and power-supply decoupling strongly influence the MAX109's performance. At a 2.2GHz clock frequency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections and adversely influence the dynamic performance of the ADC. Therefore, closely follow the grounding and power-supply decoupling guidelines (Figure 17). Maxim strongly recommends using a multilayer printed circuit board (PCB) with separate ground and power-supply planes. Since the MAX109 has separate analog and digital ground connections (GNDA, GNDI, GNDR, and GNDD, respectively), the PCB should feature separate analog and digital ground sections connected at only one point (star ground at the power supply). Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. High-speed signals, including clocks, analog inputs, and digital out-
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Differential Nonlinearity (DNL)
VCCO
GNDD
330F
33F
0.1F
0.01F
0.01F
0.01F
0.01F
VCCI
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX109, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Offset Error
GNDI 330F 33F 0.1F 0.01F 0.01F 0.01F 0.01F
VCCA
GNDA
330F
33F
0.1F
0.01F
0.01F
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the mid-scale MAX109 transition occurs at 0.5 LSB above mid scale. The offset error is the amount of deviation between the measured mid-scale transition point and the ideal midscale transition point.
Bit Error Rates
VCCD
GNDD
330F
33F
0.1F
0.01F
0.01F
0.01F
0.01F
VEE
1N5817 GNDI
Errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. Here, the magnitude of the error depends on the location of the comparator in the comparator network. If it is the comparator for the MSB, the error will reach full scale. The MAX109's unique encoding scheme solves this problem by limiting the magnitude of these errors to 1 LSB.
0.01F
330F
33F
0.1F
0.01F
0.01F
0.01F
NOTE: LOCATE ALL 0.01F CAPACITORS AS CLOSE AS POSSIBLE TO THE MAX109 DEVICE.
VCCA = +4.75V TO +5.25V VCCD = +4.75V TO +5.25V VCCI = +4.75V TO +5.25V VCCO = +3.0V TO VCCD VEE = -4.75V TO -5.25V
Dynamic/AC Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first 15 harmonics (HD2 through HD16), and the DC offset: SNR = 20 x log (SIGNALRMS / NOISERMS)
Figure 17. MAX109 Decoupling and Bypassing Recommendations
supply for the chip should have its own 0.01F capacitor, which should be placed as close as possible to the MAX109 for optimum high-frequency noise filtering.
Static/DC Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX109, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
26
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus
______________________________________________________________________________________
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
MAX109
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is calculated from a curve fit referenced to the theoretical full-scale range.
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones, fIN1 and fIN2. The individual input tone levels are at -7dBFS. The third-order intermodulation products are located at 2 x fIN1-fIN2, 2 x fIN2-fIN1, 2 x fIN1+fIN2, and 2 x fIN2+fIN1.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 15 harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + ... + V162 THD = 20 x log V1
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
where V1 is the fundamental amplitude, and V2 through V16 are the amplitudes of the 2nd- through 16th-order harmonics (HD2 through HD16).
______________________________________________________________________________________
27
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
MAX109
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 25x25 / 27x27 MM SBGA 192 / 256 BALLS, 1.27 MM PITCH
21-0073
E
1 2
28
______________________________________________________________________________________
SUPER BGA.EPS
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX109
PACKAGE OUTLINE, 25x25 / 27x27 MM SBGA 192 / 256 BALLS, 1.27 MM PITCH
21-0073
E
2 2
Note: The MAX109 is packaged in a 27mm x 27mm, 256 SBGA package.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
CARDENAS

▲Up To Search▲

Price & Availability of MAX109EHF-D

	To Download MAX109EHF-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .